MIT 6.375 Project Viterbi Decoder

The use of forward error correction (FEC) technique is known to be an e ective way to increase the reliability of the digital communication and to improve the capacity of a channel. Convolutional encoder at the transmitter associated with the Viterbi decoder at the receiver has been a predominant FEC technique because of its high e ciency and robustness. However, the Viterbi decoder consumes large resources due to its complexity, and the decoding load has increased with newer communication standards; as a result, the hardware solution has become crucial for higher performance and cost e ectiveness. A Viterbi Decoder for IEEE 802.16 WiMax Standards (constraint length K = 7, supporting rates of 1/2, 2/3, 3/4, 5/6) has been implemented in Bluespec on an FPGA. The design is based on MATLAB source code of Viterbi decoder. The decoder throughput has been boosted by using parallel and pipelined architecture to reach over 150Mb/s. Bluespec and FPGA played a key role in that it remarkably reduces design e ort as well as veri cation time through high-level synthesis.